Information on running neuronal simulations on FPGAs

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### Background

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### Bluehive project

For more details, see here: http://www.opensourcebrain.org/projects/bluehive-showcase

### Si Elegans project

For more details, see here: http://www.si-elegans.eu/

### BrainFrame Project

The goal of the BrainFrame effort is creating a back-end hardware library of designs emulating the Cerebellum system, based on reconfigurable (DFEs in this case) platforms, as a practical simulation solution for real-time neuro-scientific experiments. Eventually also make a library of generic constructs that can used on general neuron model development. This backend will be combined with a PyNN front-end to implement  the BrainFrame tool-flow.  PyNN, a Python-based, simulator-independent language for specification of brain models, is a widely known and used framework by computational neuroscientists. PyNN is capable of achieving high-speed simulation and it already offers a common interface to popular simulation platforms such as NEURON and NEST as well as newly developing ones that show great future potetial, such as NeuroML.

For More Details See here: http://erasmusbrainproject.com/index.php/themes/brainframe

### Other systems

[A Large-Scale Spiking Neural Network Accelerator for FPGA Systems Systems](http://www.async.org.uk/nerh2012/nerh2012_submission_2.pdf)

Kit Cheung, Simon R. Schultz, Wayne Luk, Imperial College London

[A Biologically Plausible Real-time Spiking Neuron Simulation Environment Based on a Multiple-FPGA Platform](http://dl.acm.org/ft_gateway.cfm?id=2082176&ftid=1071641&dwn=1&CFID=223379110&CFTOKEN=73391392)

Shufan Yang, TM McGinnity, University of Ulster

[An FPGA-based approach to high-speed simulation of conductance-based neuron models](http://link.springer.com/article/10.1385%2FNI%3A2%3A4%3A417)

E. L. Graas, E. A. Brown, Robert H. Lee, Emory University/Georgia Institute of Technology

[FPGA-based Biophysically-Meaningful Modeling of Olivocerebellar Neurons](http://erasmusbrainproject.com/media/PDFresources/PublicationsBrainFrame/FPGA2014.pdf)

Georgios Smaragdos, Sebastian Isaza, Martijn Van Eijk, Ioannis Sourdis and Christos Strydis